Welcome to the RISC‑V Graphical Datapath Simulator! This is a 32‑bit, single-cycle implementation of RISC‑V. All the 32-bit integer instructions are supported except the syscall and concurrency related instructions and auipc. The datapath is closely based on the design described in Computer Organization and Design RISC‑V Edition

You can write RISC‑V assembly, set the initial registers and initial data memory, and then step through the demo. You can input registers and memory as hex, unsigned decimal, or signed decimal by using the dropdowns in the editors. Use the "Examples" dropdown to select a pre-made assembly program to run. While the demo is running, you can use the side pane to view the current memory and registers. Labels and tooltips on the diagram will show the state of each wire and component.

You can view the source or contribute on GitHub.